International Conferences


P. Saravanan, B. S. Priyadarshini, P. V. Kanna and P. Vaishnavi, "Hardware Accelerator for Dual Standard Deblocking Filter," 2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID), 2021, pp. 210-215,2021, DOI:10.1109/VLSID51830.2021.00041  


M. Priyadharshini and P. Saravanan, "An Efficient Hardware Trojan Detection Approach adopting Testability based Features," 2020 IEEE International Test Conference India, 2020, pp. 1-5,2020,DOI:10.1109/ITCIndia49857.2020.9171786  


P.Saravanan,S.SubhaRani,S.Shanthi Rekha,H.S.Jatna,"An Efficient ASIC Implementation of CLEFIA Encryption/Decryption Algorithm with Novel S-Box Architectures ",2019 IEEE 1st International Conference on Energy, Systems and Information Processing, ICESIP 2019,July 04 – 06, 2019, DOI:10.1109/ICESIP46348.2019.8938329  

A.Uma,C.Selvagangai,P.Kalpana " Design of Chopper Stabilized Preamplifier for ECG monitoring System",IEEE 4th International Conference on  Devices, Circuits and Systems (ICDCS),pp.126-129,March 2018,DOI:10.1109/ICDCSyst.2018.8605168  


M. Elangovan and K. Gunavathi, "Stability Analysis of 6T CNTFET SRAM Cell for Single and Multiple CNTs," 2018 4th International Conference on Devices, Circuits and Systems (ICDCS), 2018, pp. 63-67,2018, DOI :10.1109/ICDCSyst.2018.8605154

SubramaniyamD,Ramesh .J,”FPGA implementation of variable bit rate OFDM transceiver system for wireless applications”,Proceedings of IEEE International Conference on Innovations in Electrical, Electronics, Instrumentation and Media Technology, ICIEEIMT 2017Volume 2017-January, Pages 343 – 346,21,2017, DOI :10.1109/ICIEEIMT.2017.8116863


E. Sugitha, M. Santhanalakshmi  andManoj Kumar Srinivasan "Modeling and Simulation of phase-locked loop using verilog-A" International Conference on Advancements in Automation, Robotics and Sensing, PSG College of Technology, 23 -24 June 2016.

K.Divya and M. Santhanalakshmi   "A 14-GS/s, 3-bit, At-speed Testable ADC and DAC Pair in 0.18μm CMOS" Second International Conference on Emerging Enhancement in Engineering and Technology, IndraGanesan College Of Engineering, Tiruchirappalli, 18-19 March 2016.

 M. Santhanalakshmi and K. Yasoda, "Verilog-A implementation of energy-efficient SAR ADCs for biomedical application" 19th International Symposium on VLSI Design and Test (VDAT), 2015, abad, pp. 1-6 is indexed in IEEEXplore,2015, DOI: 10.1109/ISVDAT.2015.7208139


K.R.RadhaKrishnan , S.Subha rani, "Clock skew optimizied VLSI architecture for zero frequency filter",2nd IEEE International Conference on VLSI Systems, Architecture, Technology and applications (VLSI SATA 2016) Amrita VishwaVidyapeetham University,Bengaluru,10th-12th January 2016,DOI: 10.1109/VLSI-SATA.2016.759303


HemaChitra S., "A High Speed Blowfish Cryptographic Algorithm For Hardware Security Module In Mobile Devices", International Conference on Advancements in Automation, Robotics and Sensing, Department of RAE, PSG College of Technology, Coimbatore, June 22-24, 2016.



Copyright © 2012 PSG College of Technology