Uma, A , Kalpana, P, "ECG Noise Removal Using Modified Distributed Arithmetic Based Finite Impulse Response Filter", Journal of Medical Imaging and Health Informatics, Volume 11, Number 5, May 2021, pp. 1444-1452(9),2021, DOI: 10.1166/jmihi.2021.3770
Uma, A., Kalpana, P, "Area efficient folded undecimator based ECG detector", Scientific Reports, Vol 11, 2021 , DOI:
10.1038/s41598-021-82231-2
ShanthiRekha, S., Saravanan, P,”Power Analysis Attack Resilient Block Cipher Implementation Based on 1-of-4 Data Encoding”,ETRIJournal,Wiley 2021, DOI: 10.4218/etrij.2020-0175
S UdayaShankar,PKalpana, "Recycled Integrated Circuit detection using Reliability Analysis and Machine Learning algorithms", IET Computers & Digital Techniques, Vol 15, Issue 1, pp. 20–35, 2021, DOI:10.1049/cdt2.12005
M.Elangovan, K.Gunavathi,”Effect of CNTFET Parameters on Novel High Stable and Low Power:8T CNTFET SRAM Cell”, Transactions on Electrical and Electronic Materials, Korean Institute of Electrical and Electronic Material Engineers,2021, DOI: 10.1007/s42341-021-00346-9
Mythili.R,Kalpana P," Comparative Analysis of Parameter Extractor for Low-Power Precomputation Based Content Addressable Memory", Wireless Personal Communications, 2020, DOI:10.1007/s11277-019-06916-8
Mythili.R,Kalpana P " High Speed Network Intrusion Detection System (NIDS) using Low Power Precomputation Based Content Addressable Memory", Computers, Materials and Continua,Vol no61,pp1097-1107,2020, DOI:10.32604/cmc.2020.08396
M.Elangovan, K.Gunavathi, ,”High Stable and Low Power 8T CNTFET SRAM Cell”, Journal of Circuits, Systems, and Computers,Vol. 29, No. 5, 2020, DOI:10.1142/S0218126620500802
M.Elangovan, K.Gunavathi,”High Stable and Low Power 10T CNTFET SRAM Cell”, Journal of Circuits, Systems and Computers,Vol No29,No 10,2019, DOI: 10.1142/S0218126620501583
Thiruvenkadam, K.,Ramesh, J., Pillai, A.S., "Area-Efficient Dual-Mode Fused Floating-Point Three-Term Adder", Circuits, Systems, and Signal Processing, 38(1), pp. 173-190,2019,DOI: 10.1007/s00034-018-0848-y
HemaChitra .S,SarveshK,MadhuPreeetha B R," Comparison of Different Configurations of MicroBlaze Soft IP Core", International Journal of Applied Engineering Research, Volume 14,Number 8,ISSN 0973-9769,2019.
ShanthiRekha,.S,Saravanan.P,"Survey on power analysis attacks and its impact on intelligent sensor networks", IET Wireless Sensor Systems,Vol.8,Issue.6,pp.295-304,2018,DOI:10.1049/iet-wss.2018.5157
ShanthiRekha, S., Saravanan, P." Low-Cost AES-128 Implementation for Edge Devices in IoT Applications", Journal of Circuits, Systems and Computers, 2018, DOI: 10.1142/S0218126619500622
P.Saravanan, P.Kalpana "Novel Reversible Design of Advanced Encryption Standard Cryptographic Algorithm for Wireless Sensor Networks", Wireless Personal Communications,Volume 100, Issue 4, pp 1427-1458, 2018, DOI:10.1007/s11277-018-5647-z
Umapathi K, MeenakshiSundaram N, Kalpana P ,”The impact of the modified Poisson-Boltzmann model on protein bound to a lipid coated silicon nanowire field effect transistor biosensor in an electrolyte environment" International Journal of Physics and Chemistry of Liquids, Pages 1-11, 2018, DOI : DOI:10.1080/00319104.2018.1464162
Umapathi K, MeenakshiSundaram N &Kalpana P," Investigation of the effect of finite-sized ions on the nanowire field-effect transistor in electrolyte concentration using a modified Poisson-Boltzmann model", Physics and Chemistry of Liquids,Volume 56, Issue 2, 4 Pages 231-240, March 2018. DOI : DOI:10.1080/00319104.2017.1324573
M.Santhanalakshmi, A.Ashna "An Improved Folded Cascode Amplifier With Low Power Current Mirror Circuits "International Journal of Pure and Applied Mathematics" Volume 118 No. 10,pp.45-50,2018, DOI: 10.12732/ijpam.v118i10.6
Mahalakshmi A, 'Design of Testable Reversible Toggle Flip Flop', International Journal of Electronics, Electrical and Computational System, 2017.
Sivashankari T and Priyadharshini N, 'Comparison of Low Power Scan Chain Architectures', International Journal of Electrical and Electronics Engineers, Vol. 9 Issue 1, 2017.
P.Saravanan, P.Kalpana," A novel approach to attack smartcards using machine learning method", Journal of Scientific and Industrial Research,Volume 76, Issue 2, Pages 95-99, 2017.
S. HemaChitra, R. Yogeshwaran, " VLSI Implementation of RSA Cryptography using Fractional Chebyshev Polynomials", Asian Journal of Research in Social Sciences and Humanities Vol. 7, No. 3, pp. 43-60, 2017,DOI: 10.5958/2249-7315.2017.00159.9
M. Jotheeshkumar and S. HemaChitra 'Verilog Implementation of Optimized Elliptic Curve Crypto Processor for FPGA platform and its Performance analysis', International Journal For Trends in Engineering & Technology, Volume 15 Issue 1, 2016.
Venkateswari, R, Subha Rani, S. and Rajalakshmi, K. 'An ultra low power MICS band receiver for implantable wireless body area networks', International Journal of Information and Communication Technology, Inderscience, Vol. 8, Nos. 2/3, pp.184–197,2016. DOI: 10.1504/IJICT.2016.074845
P. Saravanan, P. Kalpana A novel approach to design A5/1 stream cipher using power analysis attack resistant reversible logic gates by International Journal of Enterprise Network Management (IJENM), Vol. 7, No. 1, 2016. DOI: 10.1504/IJENM.2016.075176
K.Divya And M. Santhanalakshmi "A 14-GS/S, 3-Bit, At-Speed Testable ADC and DAC Pair In 0.18μm CMOS" International Journal of Advanced Research In Management, Architecture, Technology & Engineering, Vol.2 pp.33-39, 2016.
M.Santhanalakshmi, " A CMOS lock in amplifier for low power biomedical applications", International Journal of biomedical Engineering and Technology", Volume No.1,2016,DOI:10.1504/IJBET.2016.074111
P. Kalpana and P.Saravanan, "Performance Analysis of Reversible Finite Field Arithmetic Architectures Over GF(p) and GF(2m) in Elliptic Curve Cryptography", Journal of Circuits, Systems and Computers World Scientific,vol.24,no.8,pp. 0218-1266, 2015. DOI: 10.1142/S0218126615501224
A.Uma," Design of Low power 2-4 compressor based 4-bit DADDA multiplier using two phase clocking adiabatic logic", International Journal for trends in Engineering and Technology (IJTET), Vol.14,issue 01,2016
M.Jotheeshkumar,S.Hemachitra,"verilog implementation of optimized Elliptic curve crypto processor for FPGA Platform and its performance analysis", International Journal for trends in Engineering &Technology,Volume 1,issue 1,PP 36-42,2016.
S.HemaChitra and S.Naveenkumar, "A Synthesis flow of Behavioural level Designs in SystemC for FPGA implementation", International Journal of Applied Engineering Research, Research India Publications, Vol. 10 No.29, 2015.
S.HemaChitra and S.Nikilla, " A Survey On Routing Intelligence In Network-On-Chip Architecture For Real-Time Communication Services" International Journal of Applied Engineering Research Research India Publications, Vol. 10 No.29, 2015.
P. Kalpana and P.Saravanan, "A Novel Implementation of SRAM PUF for Secure Applications", International Journal of Applied Engineering Research Research India Publications, vol. 10, no. 55, pp. 658-662, 0973-4562, 2015.
S.AllinChriste and M.Balaji, "FPGA Implementation of 2D Wavelet Transform of Image Using Xilinx System Generator", International Journal of Applied Engineering Research, Research India Publications, Volume:10, Pg.No-22463-22466, 2015.
S.AllinChriste and R.Ayswarya, "Hardware-Sofware Co-design Approach of AES Algorithm using Altium Nano Board", International Journal of Applied Engineering Research, Research India Publications, Volume:10, Issue No.29, Pg.No-22425-22430, May 2015.
M.Santhanalakshmi andK.Yasoda, "Verilog-A Implementation of Energy-Efficient SAR ADCs for Biomedical Application", International Journal of Applied Engineering Research Research India Publications, Volume : 10, No.29, Pg.No- 22359-22363, 2015.
K.Rajalakshmi and A.Kandaswamy, "Reconfigurable FIR architecture for the filter bank of speech processor in Cochlear Implant", International Journal of Applied Engineering Research Research India Publications, Vo. 10.29 ,2015.
P. Kalpana and P.Saravanan,"An energy efficient XOR gate implementation resistant to power analysis attacks", Journal of Engineering Science and Technology,Volume 10, Issue 10, Pages 1275-1292, 2015.
P. Saravanan and P. Kalpana, "Energy Efficient Reversible Building Blocks Resistant To Power Analysis Attacks," Journal of Circuits, Systems and Computers, vol. 23, no. 9, pp. 1450127-1 - 1450127-40.2014.
K.Rajalakshmi and A.Kandaswamy, "Folded Architecture for Digital Gammat one filter used in speech processor of Cochlear Implant", International Journal ETRI Journal, Vol.35, No.4, 2013.
U. Saravanakumar and R. Rangarajan, "Energy and throughput analysis of routing algorithms for 2D mesh Network on chip", Procedia Engineering, vol. 30, pp. 144- 151, ISSN: 1877-7058,2012.
U. Saravanakumar and R. Rangarajan, "Performance Explorations of Multicore Network on Chip Router", International Journal of Simulation: Systems, Science and Technology, vol. 13, no. 1, pp. 36-42,2012.
U. Saravanakumar and R. Rangarajan, "Design and performance evaluation of on chip network routers", Journal of Theoretical and Applied Information Technology, vol. 52, no. 2, pp. 211-218, 2013, ISSN: 1992-8645.
U. Saravanakumar and R. Rangarajan, "Simulation and analysis of multicast routing algorithm for 2-D mesh network on chip", Asian Journal of Scientific Research, vol. 6, no. 4, pp.754-762, 2013.
U. Saravanakumar, K. Rajasekar and R. Rangarajan, "Implementation of Scheduling Algorithms for On Chip Communications", International Journal of Computer Applications, vol. 62, no. 14, pp. 35-38, 2013
U. Saravanakumar, R. Rangarajan, R. Haripriya, R. Nithya and K. Rajasekar, "Cluster based hierarchical routing algorithm for network on chip", Circuits and Systems, vol. 4, pp. 401-406, 2013
S. P. Vimal, M. Kasiselvanathan and U. Saravanakumar, "A new SLM and PTS schemes for PAPR reduction in OFDM systems", International Journal of Advanced Research Computer Communication Engineering, vol. 2, pp. 4236-4240
2013
M.Santhanalakshmi, P.T.Vanathi, "Implantable Neural Signal Amplifier for Epileptic Seizure Prediction".Procedia Engineering, Elsevier Ltd., 383426-3433, 2012.
M.Santhanalakshmi, P.T.Vanathi "A fully Integrated Neural signal acquisition amplifier for Epileptic seizure prediction" International Journal of Electrical and Electronics Engineering (IJEEE), Vol-1 Iss-4 , 2012.
K.Rajalakshmi, A.Kandaswamy "A fractional delay FIR filter based on Lagrange Interpolation of farrow structure" International Journal of Electrical and Electronics Engineering (IJEEE) Vol-1 Iss-4, 2012.
K.Rajalakshmi, A.Kandaswamy, 'VLSI Architecture of Digital Auditory Filter for Speech Processor of Cochlear Implant" International Journal on Computer Applications, 39(7):19-22, Foundation of Computer Science, New York, USA,BibTeX,2012.
S.AllinChriste, M.Vignesh, Dr.A.Kandaswamy, 'An efficient FPGA implementation of MRI image Filtering and tumor characterization using Xilinx system generator" International Journal of VLSI design and Communication Systems ,Vol.2,No.4, 2011.
M.SanthanaLakshmi, P.T Vanathi 'An improved OTA for a 2nd order Gm-C Low Pass Filter" European journal of Scientific research, Vol. 66, No.1, pp. 75-84,2011.
P.Saravanan,N.Renukadevi,G.Swathi.P.Kalpana, "A highthroughput ASIC implementation of configurable AES processor' International journal of Computer applications, 2011.
N.M. Sivamangai,K. Gunavathi. , 'A Low Power SRAM Cell with High Read Stability', ECTI Transactions on Electrical Eng., Electronics, and Communications, Vol. 9, No. 1, pp. 16-22,2011.
N.M. Sivamangai,K. Gunavathi , 'Design For Test Technique for Leakage Power Reduction in Nanoscale Static Random Access Memory', Journal of Computer Science, Vol. 7, No. 8, pp. 1252-1260,2011.
N.M. Sivamangai,K. Gunavathi. , 'Fault Detection in SRAM Cell Using Wavelet Transform Based Transient Current Testing Method', International Journal of Latest Trends in Software Engineering (IJLTSE), Vol. 1, No. 1, pp. 20-27,2011.
P.Kalpana ,K.Deepalakshmi , "Fault based testing of Low Noise Amplifiers", CiiT, International journal of wireless communication, 2010
M.SanthanalakshmiP.T.Vanathi, "An improved low voltage, low power class AB operational transconductance amplifier for mobile applications", International journal of computer and network security, Vol 2 No 5, 2010
M.Santhanalakshmi "Second Order Gm-C Low Pass Filter for mobile Applications" International Journal of Electronics & telecommunication and instrumentation Engineering, Vol. 3, No 1,PP 09-14,2010
N.M. Sivamangai, K. Gunavathi,P. Balakrishnan , 'A BICS Design to Detect Soft Error in CMOS SRAM', International Journal on Computer Science and Engineering (IJCSE), Vol. 2, No. 3, pp. 734-740, 2010.
M.SanthanalakshmiP.T.Vanathi, "A low power Gm-C low pass filter for mobile applications, Journal of scientific & industrial research, vol69,pp 750-755,2010,
M.Santhanalakshmi "Design of Biomedical Op amp" Journal of computer science,Vol. 5, No. 1 Nov-Dec-2010, PP 63-69,2010
Ramesh J., Gunavathi K. , 'A Novel Linear Ramp Generator for Analog and Mixed Signal Built-In Self-Test Applications', International Journal of Electrical Engineering and Embedded Systems, Issue 1, pp. 21-32,2010.
GunavathiK,Sampath. P , 'A 900 MHz Image Reject Receiver with SS-LMS Calibration', International Journal of Recent Trends in Engineering, Vol.2, No.6, pp.53-57, 2009.
Gunavathi K. Sampath. P, C.M.Preethi , 'An Improved 70MHz CMOS Gm-C 2nd Order Band Pass Filter for Wireless Systems', International Journal on Electronic and Electrical Engineering (IJEEE), Vol.6, No.9, pp. 6-11, 2009.
P.Kalpana,K.Gunavathi, " Test generation based fault detection in Analog VLSI circuits using Neural Networks", ETRI Journal,pp 209-214,2009,
P.Ramanathan, P.T.Vanathi , 'Power Delay optimized adder for Multiply and Accumulate Units', International Journal of Digital Signal Processing, Vol. 9, Issue 1, pp.11-17, 2009.
P.Ramanathan, P.T.Vanathi , 'High Speed Multiplier Design using Decomposition Logic', Serbian Journal of Electrical Engineering, Vol.6, No.1, pp.33-42, 2009.
P.Ramanathan, P.T.Vanathi , 'A Novel Power Delay Optimized 32-bit Parallel Prefix Adder for High Speed Computing', International Journal of Recent Trends in Engineering, 2009.
P.Ramanathan,P.T.Vanathi , 'Hybrid Prefix Adder Architecture for Minimizing the Power Delay Product', International Journal of Electronics, Circuits and Systems, Vol.3, No.1, pp.66-70, 2009.
P.Ramanathan, P.T.Vanathi, T.S.Keirthana,N. SindhuMaheswari , 'Comparative Analysis of Power Delay Product Between Different Families with Achievement of Reduction using Decomposition Algorithm', International Journal of Power, Control, Signal and Computation, Vol.1, No.1, pp.41-46.,2010.
N.M. Sivamangai ,K. Gunavathi , 'High Reliable Self Repairable Architecture for SRAM', International Journal on Programmable Devices, Circuits and Systems (ICGST-PDCS), Vol. 9, Issue 1, pp.1-8, 2009.
Ramesh J., Vanathi P.T ,Gunavathi K. , 'Fault Classification in Phase Locked Loops using Back Propagation Neural Networks', International Journal of Soft Computing Applications (IJSCA), No. 3, pp. 77-95.,2008
Ramesh J., Vanathi P.T ,Gunavathi K. , 'Fault Classification in Phase Locked Loops using Back Propagation Neural Networks', Electronics and Telecommunication Research Institute (ETRI) Journal, Vol. 30, No. 4, pp. 546-554. 2008
P.Kalpana, K.Gunavathi, " Wavelet based fault detection in analog VLSI circuits using neural networks", Journal of Applied soft computing, Elsevier science, pp 1592-1598,2008,
P.T.Vanathi, J.Ramesh, K.Gunavathi "Fault Classification in Phase Locked Loops using Back Propagation Neural Networks" in the International Journal of Soft Computing Applications, Issue 3, Page 77-95,2008
Ramesh J,Gunavathi K. , 'A Novel Built-In Self-Test Architecture for Charge- Pump Phase Locked Loops', International Journal on Programmable Devices, Circuits and Systems (ICGST-PDCS), Vol. 7, Issue 1, pp.1-6.,2007
P.Kalpana,K.Gunavathi, "A novel implicit parametric fault detection method for analog/mixed signal circuits using wavelets", International journal on Programmable devices and circuits , vol 7, 2007.
M.Santhanalakshmi ,"Optimizing CMOS Circuit for Performance Improvements using Adiabatic Logic" Information Technology, Vol 6 No 3, 2007
P.Kalpana, K.Gunavathi, "A novel wavelet based testing method for analog VLSI circuits using pseudorandom patterns", AMSE Journal, France, vol 79, 2006.
P.Kalpana,K.Gunavathi , "Enhancing fault detection sensitivity of oscillation based test method using wavelets" Journal of system science and engineering, Vol 12&pp 62-70, 2005.(System society of India).
P.Kalpana,K.Gunavathi, "Behavioral Modeling And Fault Simulation Of System On Chips" acad journal &Vol 13,2004.
P.Kalpana,K.Gunavathi , "Fault oriented Test Pattern Generator for Digital to Analog converters" acad journal &vol 13,2004.
LalithaKathambari D, Kalpana P and Uma A, 'Design of Low power successive approximation ADC using segmented architecture', National Journal of Technology, 2017.
Dinesh R and P Saravanan, 'A countermeasure for leakage power analysis attacks on cryptographic processor', National Journal of Technology, 2017.
Subha Rani S, Radhakrishnan K R, Varun Power Aware Simulation And Verification of 16-Bit ALU Using Unified Power Format Standards', National Journal of Technology 2017
S.HemaChitra,N.Vinay Reddy," A Pipelined Fused Processing Unit for DSP Applications", National Journal of Technology, Volume:11 Issue No.1, 2015
K.Divya And M. Santhanalakshmi "A 4-bit At-Speed Testable Two step Flash ADC and DAC Pair In 0.18μm CMOS", National Journal of Technology, Vol. 13, Iss. 3 Sep 2017
S.AllinChriste and M.Balaji, " HW/SW Co-design of various Image Processing Algorithms Using Xilinx System Generator", National Journal of Technology, ISSN: 0973-1334, Volume:11 Issue No.1, Pg.No-1-9, 2015
K.Rajalakshmi, SwathiGandi and A.Kandaswamy," Design of variable fractional delay based FIR filter', National journal of Technology, 2013
U. Saravanakumar, R. Rangarajan and K. Rajasekar, "Hardware Implementation of Pipeline Based Router Design for On-Chip Network", ICTACT Journal on Communication Technology, vol. 3, no. 4, pp. 646-650, 2012
P.Ramanathan and P.T.Vanathi, 'Novel Decomposition Algorithm for Power Delay Optimization in Wallace and Carry Save Multipliers', National Journal of Technology, 2009.
J.Saranya, P.Kalpana," Testing of Digital VLSI circuits for resistive bridging faults", National journal of Technology, vol 3, 2007
M.Santhanalakshmi , "Improved Adiabatic Logic for Efficient Charge Recovery" National Journal of Technology of PSG College of Technology, Coimbatore-4,Vol 2 & No 2 ,2006.
P.Vijayakumar,K.Gunavathi , "Performance Improvement of CMOS Circuits with concurrent Application of Resonant Charging and Retiming Algorithm" National Journal of Technology & 2005.